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Cypress Semiconductor /psoc63 /FLASHC /FM_CTL /FM_CTL

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Interpret as FM_CTL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0FM_MODE0FM_SEQ 0DAA_MUX_SEL0 (IF_SEL)IF_SEL 0 (WR_EN)WR_EN

Description

Flash macro control

Fields

FM_MODE

Flash macro mode selection: ‘0’: Normal functional mode. ‘1’: Sets ‘pre-program control bit’ for soft pre-program operation of all selected SONOS cells. the control bit is cleared by the HW after any program operation. ‘2’: Sets … ‘15’: TBD
FM_SEQ

Flash macro sequence select: ‘0’: TBD ‘1’: TBD ‘2’: TBD ‘3’: TBD
DAA_MUX_SEL

Direct memory cell access address.
IF_SEL

Interface selection. Specifies the interface that is used for flash memory read operations: ‘0’: R interface is used (default value). In this case, the flash memory address is provided as part of the R signal interface. ‘1’: C interface is used. In this case, the flash memory address is provided by FM_MEM_ADDR (the page address) and by the C interface access offset in the FM_MEM_DATA structure.
WR_EN

‘0’: normal mode ‘1’: Fm Write Enable

Links

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Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data